I. Field of the Invention
The present invention relates in general to the fabrication of a semiconductor device, and more particularly to the fabrication of a power IC semiconductor structure.
II. Description of Related Art
Fabrication processes have recently been developed that retain the standard steps used for the fabrication of discrete power devices but expand these steps to include the fabrication of IC control devices. Several high-powered technologies can be used in these IC fabrication processes that take advantage of vertical power device fabrication steps to form standard CMOS devices at the same time that the power device is made. This combination of wafer fabrication steps retains the desired features of both technologies and offers a cost-effective, space saving alternative, as well as bringing new performance features to the system design.
Heretofore, the combination of the power device with the control circuitry required a relatively lengthy fabrication process. Typically, more than ten mask layers have been required to fabricate a device combining power circuitry and control circuitry.
It is therefore an object of the present invention to provide an improved method of fabricating a semiconductor device which is not subject to the foregoing problems and disadvantages.
It is an additional object of the present invention to provide an improved method of manufacturing a simple power IC structure which may include self-aligned CMOS.
It is another object of the present invention to provide an improved method of manufacturing a semiconductor device in which a high-density DMOSFET may be integrated with a 20-volt or 5-volt CMOS IC.
It is a further object of the present invention to provide an improved method of fabricating a power IC structure which may have relatively high density and/or low "on" resistance.
It is another object of the present invention to provide an improved method of fabricating a power IC structure in which a 50 V lightly doped chain N channel MOSFET may be integrated with a 20-volt depletion mode N channel MOSFET.
It is a further object of the present invention to provide an improved method of fabricating a basic structure for a power IC with high density digital IC capability.